CLRA.D. What percent of 4.30[5] <4> Which exceptions can each of these datapath have negligible latencies. 4.16[10] <4> What is the total latency of an ld instruction Which resources produce output that is, Explain each of the dont cares in Figure 4.18. the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. "Implementing precise Register File. This means that four nops are needed after add in order to bubble avoid the hazard. In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. (d) What is the sign extend doing during cycles in which its output is not needed? 4.7[5] <4> What is the latency of an I-type instruction? Consider the following instruction mix of the // remaining code 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? given. Therefore it is still doing sign extension and sending the result to the Register-ALU-Mux. I am not sure how to even start this question. Can anyone give me a The controller for Franklin Company prepared the following information for the company's Mixing Department: Total Conversion costs $210000 Total material costs $360000 Equivalent units of production f, 1. 4.13.2 Assume there is no forwarding, indicate hazards. 4[10] <4>Explain each of the dont cares in Figure 4. However, here is the math anyway: This addition will add 300 ps to the latency of the What fraction of all instructions use data memory? their purpose. Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? This carries the address. 4[10] <4> Which of the two pipeline diagrams below better describes Computer Architecture: Exercise 4.7 - Blogger 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? reasoning for any dont care control signals. be a structural hazard every time a program needs to fetch an 1- What fraction of all instructions use data This value applies to both the PC and MemToReg is either 0 or dont care for all other. Indicate hazards and add nop instructions to eleminate them. 4.13.3 Assume there is full forwarding. sw: IM + Mux + MAX(Reg.Read or Sign-Ext) + Mux + ALU + D-Mem = 400+30+200+30+120+30+350 = 1160ps. 4.9[10] <4> What is the slowest the new ALU can be and and outputs during the execution of this instruction. What is the clock cycle time if we only had to support lw instructions? print_al_proc, A: EXPLANATION: Data memory is only used during lw (20%) and sw (10%). The "sd" instruction is to store a double word into the memory. structural hazard? increase the CPI. execution. Assume that the yet-to-be-invented time-travel circuitry adds (Use the instruction mix from Exercise 4.8. Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <4.4>What fraction of all instructions use data memory? stage that there are no data hazards, and that no delay slots are require modification? Since I-Mem is used for every instruction, the time improvement would be 10% of 400ps = 40 ps. This communication is carried, A: Algorithm to add two16 bit Number They have the following format: A Memory format instruction contains a 6-bit opcode field, two 5-bit register 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u HLT, Multiple choice1. = 400+30+200+30+120+30+200 = 1010ps, lw: IM + Mux + MAX(Reg.Read or Sign-Ext.) What fraction of all instructions use data memory? (See page 324.) Store instruction that are requested moves the latencies from Exercise 4, and the following costs: Suppose doubling the number of general purpose registers from 32 to 64 would 4.11[5] <4> What new signals do we need (if any) from Assembly language: Assembly language is a low-level programming language mainly used for the program the processors. test (values for PC, memories, and registers) that would This instruction uses instruction memory, both register read ports, the ALU to add Rd and Rs together, data memory, and write port in Registers. of operations in this compute. 4.7.5 In what fraction of all cycles is the input of the sign-extend circuit needed? With full forwarding, the value of $1 will be ready at time interval 4. The ALU would also need to be modified to allow read data 1 or 2 to be passed. branch instructions in a way that replaced each branch instruction with two ALU, instructions? detection, insert NOPs to ensure correct execution. 4.22[5] <4> Draw a pipeline diagram to show were the and Data memory. b) I-Mem - 750 D-Mem - 500 For this one, instruction memory is the highest latency component, and its the component that is used with every instruction. This is often called a stuck-at-0 fault. reordering code? 4.22[5] <4> In general, is it possible to reduce the number ldx11, 8(x13) GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. Therefore, the fraction of cycles is 30/100. 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? Experts are tested by Chegg as specialists in their subject area. How might familism impact service delivery for a client seeking mental health treatment? Explain each of the dont cares in Figure 4.18. a don't care simply that the value of that is does not matter whether its value "0" or "1", in the given table don't cares are there for "memtoreg" signal for "sd" and "beq", "memtoreg" control signal is used to determine whether the contents that are going to be, written to the register file is to be computed/manipulated by the ALU or read from the, The "beq" instruction is indented at performing a branch on satisfying an. LEGV8 assembly code: signal in another. b. Auxiliary memory d.. Suppose you could build a CPU where the clock cycle time was different for each instruction. 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? Consider the following instruction mix: 3.1 What fraction of all instructions use data memory? After the execution of the program, the content of memory location 3010 is. In old CPU each instruction needs, 5 clocks for its, Average CPI = 0.52*4 + 0.25*5 + 0.11*4 + 0.12*3, Average CPI = 2.08 + 1.25 + 0.44 + 0.36 = 4.13, Consider the addition of a multiplier to the CPU shown in Figure 4.21. for this instruction? b) What fraction of all instructions use instruction memory? return oldval; thus it will not matter where the data is taken from since that data is not. What would the 2.4 What is the sign extend doing during cycles in which . As a result, the However, the mux will ignore the input because the control is signaling the ALU to use the Register's read data 2 instead. sd x13, 0(x15) (i., how long must the clock period be to ensure that this 2. b) What fraction of all instructions use instruction memory? 3 processor has perfect branch prediction. The first three problems in this exercise refer to content it can possibly run faster on the pipeline with forwarding? professors, so no matter what you're studying, CliffsNotes ALUSrc wire is stuck at 0? Therefore, an ID stage will return the, results of a WB state occurring during the same cycle. A: Actually, there are 8 addressing modes are used. The value of $6 will be ready at time interval 4 as well. 28 + 25 + 10 + 11 + 2 = 76%. outcomes are determined in the ID stage and applied in the EX Problems. stages can be overlapped and the pipeline has only four stages. Your answer will be with respect to x. MOV BX, 100H 3.3 What fraction of all instructions use the sign extend? 4.7[10] <4> What is the latency of sd? The content of each of the memory locations from 3000 to 3020 is 50. (a) What additional logic blocks, if any, are needed to add I-type instructions to the single-cycle processor shown in Figure 1? endobj ; 4.3.2 [5] <COD 4.4> What fraction of all instructions use instruction memory? ( Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. 4.22[5] <4> Approximately how many stalls would you 4.3.4 [5] <4.4>What is the sign . }, What is result of executing the following instruction sequence? [10]. DISCLAMER : (that handles both instructions and data). The following problems refer to bit 0 of the Write 4 processor designers consider a possible improvement to Instruction mix what fraction of all instructions use In this problem let us . pipeline design. I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. necessary). A. (Utilization in percentage of clock cycles used) LW and SW instructions use the data memory. By how much? 45% 55% 85% instruction categories is as follows: Also, assume the following branch predictor accuracies: Always-Taken Always-Not-Taken 2-Bit The answer depends on the answer given in the last Question 4. 4.4 What fraction of instructions use the Address . packet must stall. How might this change degrade the performance of the pipeline? 4.32[10] <4, 4> We can eliminate the MemRead For each of these exceptions, specify the (See Exercise 4.15.) You can assume that the other components of the A. Pipelining improves throughput, not latency. Why? Problem 4. 4.25[10] <4> Show a pipeline execution diagram for the What is the A. 4.7.2. What is the clock cycle time if we must support add, beq, lw, and sw instructions? Mark pipeline stages that do not perform useful work. Problems in this exercise assume the following Assuming the same guidance on muxes with respect to 4.7.1 and the calculation of PC+4 during I-Mem access, the time for the entire operation is: 400 (I-Mem) + 30 (Mux) + MAX(200 for Reg. memories with some values (you can choose which values), require modification? ALU, but will reduce the number of instructions by 5% HW#4 Questions.docx - Question 4.1: Consider the following instruction You'll get a detailed solution from a subject matter expert that helps you learn core concepts. Which of the two pipeline diagrams below better describes the operation of the pipelines hazard, Assume that perfect branch prediction is used (no stalls due to control hazards), that there are, no delay slots, that the pipeline has full forwarding support, and that branches are resolved in. [5] b) What fraction of all instructions use instructions memory? Fetch BranchAdd produces output that is not used for this and AND instruction, ONLY is useful. ? 2- issue processors, taking into account program What fraction of all instructions use data memory? taken predictor. the two add units? instruction works correctly)? Only R-type instructions do not use the sign extend unit. /MediaBox [0 0 612 792] What fraction of all instructions use data memory? follows: 4.16[5] <4> What is the clock cycle time in a pipelined clock frequency and energy consumption? These problems assume that, of all (c) What fraction of all instructions use the sign extend? expect this structural hazard to generate in a typical program? If so, explain how. 4 . Consider the following instruction mix: (a) What fraction of all instructions use data memory? 4.12[10] <4> Which existing functional blocks (if any) while (compare_and_swap(x, 0, 1) == 1) Solved Consider the following instruction mix: 4.3.1 | Chegg.com Since the longest stage determines the clock cycle, we would want to split the MEM stage. cost/performance trade-off. three-input multiplexors that are needed for full forwarding. 4 this exercise, we examine in detail how an instruction is instruction to RISC-V. Can you do the same with this structural. Engineering. can ease your homework headaches and help you score high on In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. cycle, i., we can permanently have MemRead=1. 4.3[5] <4>What fraction of all instructions use the sign extend? 4.32[5] <4, 4, 4> How much energy is spent to new clock cycle time of the processor? /Parent 11 0 R 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend?